The present invention relates generally to signal processing and, specifically to, digital signal compression and decompression.
Current video and still image compression and decompression schemes contain separate functional blocks for pre-processing, post-processing, inverse/forward discrete cosine transformation (IDCT/DCT) and finite impulse response (FIR) filtering. The separate blocks are currently used in such devices as high definition television and video conference devices. The data path size for the IDCT/DCT and the FIR filter is dictated by the type of application. Applications that may use low quality images, such as video conferencing can operate with smaller data paths. Applications such as HDTV require wider data paths and results in a clear and more dense picture.
An IDCT/DCT block design using distributed arithmetic is described in an Institute of Electrical and Electronics Engineers (IEEE) paper by S. I. Uramoto, et al., xe2x80x9cA 100-Mhz 2-D Discrete Cosine Transform Core Processor,xe2x80x9d IEEE Journal of Solid-State Circuits, vol. 27(4), April 1992, pp.492-499. The Uramoto paper described a DCT/IDCT distributed arithmetic processor (DAP) as a processing unit connected to a transpose random access memory (RAM), with the transpose RAM connected to other DCT/IDCT processing units. The DCT/IDCT DAP accomplished the DCT/IDCT transforms via multiply accumulator operations.
Disadvantageously, when signal compression and decompression is applied to a signal via a DCT/IDCT DAP, an additional filter (usually a FIR filter) is required. The additional FIR filter results in an increase in the total component cost of an apparatus. The production cost associated with the additional hardware is also increased because of the additional assembly tasks required for inserting and configuring the FIR filter. Accordingly, there is a need in the art for a method and apparatus for reducing production and component costs of signal compression and decompression circuits.